This application claims the benefit of Korean Patent Application No. 2000-28063, filed on May 24, 2000, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the invention
The present invention relates to semiconductor devices, and more particularly, to an impedance matching circuit for a semiconductor memory device.
2. Description of Related Art
An impedance matching circuit for a semiconductor memory device is a circuit that matches the impedance between a semiconductor memory device and an external device. A mismatch of the impedance between two signal lines or a signal line and an output driver may cause a reflected wave. Such a reflected wave results in signal distortion. To prevent the signal distortion, the impedance matching circuit is provided to match the impedance between the two signal lines or between the signal line and the output driver so that the reflected wave is absorbed.
FIG. 1 is a block diagram illustrating a conventional impedance matching circuit for a semiconductor memory device. The impedance matching circuit includes pads ZQ and DQ1 to DQn, p-channel metal oxide semiconductor (PMOS) arrays 10 and 12, an n-channel metal oxide semiconductor (NMOS) array 14, a comparator 16, a ZQ counter 18, a ZQ driver 20, data output buffer and drive units 30-1 to 30-n. The data output buffer and drive units 30-1 to 30-n include data output buffers 22-1 to 22-n and output drivers 24-1 to 24-n in such a manner that each of the data output buffer and drive units has a data output buffer and an output driver.
The PMOS array 12 and NMOS array 14 adjust their resistance values in response to a counting output signal CTQx to generate a reference voltage Vref. The reference voltage Vref may be equal to the half of a power source voltage VDDQ. The PMOS array 10 adjusts its resistance value in response to the counting output signal CTQx to generate a voltage Vzq divided by an external resistance Rzq.
The comparator 16 compares the voltage Vzq with the reference voltage Vref to generate a comparing output signal. When the voltage Vzq is higher than the reference voltage Vref, the comparator 16 generates a signal having a logic xe2x80x9chighxe2x80x9d level. When the voltage Vzq is smaller than the reference voltage Vref, the comparator 16 generates a signal having a logic xe2x80x9clowxe2x80x9d level. When a signal having a logic xe2x80x9chighxe2x80x9d level is inputted into the ZQ counter 18, an up-counting operation is performed. When a signal having a logic xe2x80x9clowxe2x80x9d level is inputted into the ZQ counter 18, a down-counting operation is performed. The ZQ counter 18 generates the counting output signal CTQx of a predetermined number of bits, and the counting output signal CTQx varies the resistance values of the PMOS array 10 and 12 and the NMOS array 14. The ZQ driver 20 drives the counting output signal CTQx from the ZQ counter 18.
Each of the data output buffers 22-1 to 22-n buffers a corresponding one of data output signal pairs DLAT1/B to DLATn/B to generate data and combines the output signal from the ZQ driver 20 and the data to generate output data. Each of the output drivers 24-1 to 24-n adjusts its resistance value in response to the output data from a corresponding one of the data output buffers 22-1 to 22-n to output data to the data input/output pads DQ1 to DQn.
FIG. 2 is a circuit diagram illustrating the PMOS arrays 10 and 12 and the NMOS array 14 of the impedance matching circuit in FIG. 1. The PMOS array 10 includes PMOS transistors P1 to P7 connected to each other in parallel between a power source voltage VDDQ and the pad ZQ. The PMOS array 12 includes PMOS transistors P8 to P14 connected to each other in parallel between the power source voltage VDDQ and a reference voltage generating node. The NMOS array 14 includes NMOS transistors N1 to N7 connected to each other in parallel between the reference voltage generating node and a ground voltage. An inverter I is provided to invert the counting output signal CTQx so that an inverted counting output signal CTQxB is provided to the PMOS arrays 10 and 12.
In the PMOS arrays 10 and 12, gate electrodes of the PMOS transistors P1, P2, P13 and P14 are connected with the ground voltage and are always xe2x80x9conxe2x80x9d, and gate electrodes of the PMOS transistors P3 to P7 and P8 to P12 are connected with the inverted counting output signal CTQxB. In the NMOS array 14, gate electrodes of the NMOS transistors N6 and N7 are connected with the power source voltage VDDQ and thus are always xe2x80x9conxe2x80x9d, and gate electrodes of the NMOS transistors N1 to N5 are connected with the counting output signal CTQx from the ZQ counter 18.
At the beginning of the impedance matching operation, the counting output signal CTQx of the ZQ counter is xe2x80x9c00000xe2x80x9d, and therefore, the PMOS transistors P3 to P12 and the NMOS transistors N1 to N5 are all turned off, so that the reference voltage Vref is divided by the PMOS transistors P13 and P14 and the NMOS transistors N6 and N7, and the voltage Vzq is divided by the PMOS transistors P1 and P2 and the resistance Rzq.
The comparator 16 of FIG. 1 performs a comparing operation with respect to the reference voltage Vref and the voltage Vzq to generate the comparing output signal to the ZQ counter 18 which performs up or down counting in response to the comparing output signal to generate the counting output signal CTQx to adjust the resistance values of the PMOS arrays 10 and 12 and the NMOS array 14.
FIG. 3 is a circuit diagram illustrating the output driver of the impedance matching circuit in FIG. 1. The output driver includes a PMOS array 32 that has PMOS transistors P15 to P21 connected to each other in parallel between a power source voltage VDDQ and an output signal generating node, and an NMOS array 34 that has NMOS transistors N8 to N14 connected to each other in parallel between the output signal generating node and a ground voltage.
In FIG. 3, references DOU and DOD denote output data pairs provided from a corresponding data output buffer. The output data pairs DOU and DOD are, for example, 6-bit data that are generated by combining the data generated by buffering the data applied to the data output buffer and the data generated by buffering the 5-bit data from the ZQ driver.
In FIG. 3, the data applied to gate electrodes of the PMOS transistors P15 to P19 is 5-bit data that is generated by combining data buffered with 5-bit data DOU that the output buffer outputs. The data applied to gate electrodes of the PMOS transistors P20 and P21 is 1-bit data DOU buffered by the data output buffer.
In the same way, the data applied to gate electrodes of the NMOS transistors N8 to N12 is 5-bit data DOD that is generated by combining data buffered with 5-bit data that the data output buffer outputs. The data applied to gate electrodes of the NMOS transistors N13 and N14 is 1-bit data DOD buffered by the data output buffer.
That is, the PMOS transistors P15 to P19 and the NMOS transistors N8 to N12 are turned on or off by the 5-bit counting control signal, and the PMOS transistors P20 and P21 and the NMOS transistors N13 and N14 are turned on or off by the 1-bit data buffered by the data output buffer.
Since the counting output signal is xe2x80x9c00000xe2x80x9d when a voltage is applied, the PMOS transistors P15 to P19 and the NMOS transistors N8 to N12 of the output driver are all turned off, so that an initial resistance value is set to become a maximum resistance value. The ZQ counter 18 can generate the counting output signal having maximum 32 steps from xe2x80x9c00000xe2x80x9d to xe2x80x9c11111xe2x80x9d.
Thus, the conventional impedance matching circuit for a semiconductor memory device has the maximum resistance value when a voltage is applied and varies the resistance value from the maximum resistance value to resistance values of maximum 32 steps when an impedance matching operation is performed.
That is, the conventional impedance matching circuit for a semiconductor memory device determines the steps of the resistance value between the maximum resistance value and the minimum resistance value by a bit number of the counter. Therefore, as the difference of the resistance values between the steps becomes large, it becomes more difficult to precisely adjust the resistance value. It is possible to precisely adjust the resistance value by reducing the difference of the resistance value between the maximum resistance value and the minimum resistance value.
However, in case of increasing the bit number of the counter, since the resistance value of the output driver is adjusted in the range from the maximum resistance value to the minimum resistance value, there is such a problem that the impedance matching is completed after undergoing many steps when the resistance value is very small.
Therefore, a need exists for an impedance matching circuit for semiconductor memory devices which precisely adjusts the resistance value without increasing the bit number of the counter.
It is an object of the present invention to provide an impedance matching circuit for a semiconductor memory device that precisely adjusts a resistance value without increasing the bit number of a counter in the impedance matching circuit.
In order to achieve the above and other objects, the present invention provides an impedance matching circuit for a semiconductor memory device. The impedance matching circuit includes an impedance detecting means for generating a voltage divided by a medium resistance value between a maximum resistance value and a minimum resistance value and an external resistance during a predetermined cycle as a first comparison voltage, and for generating a voltage divided by a resistance value varied in response to a counting output signal and the external resistance after the predetermined cycle as the first comparison voltage; a first comparing means for comparing the first comparison voltage with a reference voltage to generate a first comparing output signal; a second comparing means for comparing the first comparison voltage with the reference voltage to generate a second comparing output signal; a counting means for generating the counting output signal in response to the first comparing output signal; and a plurality of output drivers for establishing an initial resistance value in each of the output drivers in response to the second comparing output signal and for adjusting a resistance value in each of the output drivers in response to the counting output signal.
The impedance detecting means preferably includes a plurality of first pull-up transistors connected to each other in parallel between a power source voltage and a node for generating the first comparison voltage and being turned on or off in response to the counting output signal; at least one second pull-up transistor connected with the power source voltage and being turned on or off in response to an output signal of a cycle detecting means; and at least one resistor connected between the at least one second pull-up transistor and the node generating the first comparison voltage, wherein a resistance value of the at least one second pull-up transistor and the at least one resistor is established to be the medium resistance value between the maximum resistance value and the minimum resistance value.
Each of the output drivers preferably includes a plurality of third pull-up transistors connected to each other in parallel and being turned on or off in response to the counting output signal; a plurality of first pull-down transistors connected to each other in parallel and connected with the plurality of the third pull-up transistors in serial, and being turned on or off in response to the counting output signal; a fourth pull-up transistor being turned on or off in response to the second comparing output signal and connected with the plurality of the third pull-up transistors in parallel; and a second pull-down transistor being turned on or off in response to the second comparing output signal and connected with the plurality of the first pull-down transistors in parallel.
In the impedance matching circuit for a semiconductor memory device according to the present invention, the resistance value of the output driver is precisely adjusted without increasing the bit number of the counter.